1. Field of the Invention
This invention relates to a semiconductor device testing method and testing equipment, and in particular relates to an effective testing method and testing equipment for special semiconductor devices which do not operate in the power supply conducting state.
2. Description of the Related Art
Tests conducted in order to exclude semiconductor devices which undergo infant mortality failure are called burn-in tests.
FIG. 1 shows general changes in the failure rate of semiconductor devices. The horizontal axis plots the operating time, and the vertical axis shows the failure rate. FIG. 1 is generally called the “bathtub curve”; in the infant mortality period T1 during which the operating time is short, the failure rate is high, but when the infant mortality period T1 has passed the failure rate stabilizes at a low level, with failures occurring only randomly, in what is called the random failure period T2. Finally, as the limit of the normal operating life is approached, the failure rate increases; this period is called the wear-out period T3.
Thus when a semiconductor device operates past the infant mortality period T1, the failure rate declines greatly; hence at time of shipment, the semiconductor device is inserted into a thermostatic chamber controlled at an elevated temperature and current is passed to perform accelerated testing and promote infant mortality failures, and those semiconductor devices which may fail in the infant mortality period T1 are excluded. This is called a burn-in test. Such burn-in tests are described in for example Japanese Patent Laid-open No. 11-142471 and Japanese Patent Laid-open No. 7-5231.
In the burn-in testing method described in Japanese Patent Laid-open No. 11-142471, a power supply voltage and input test pattern are supplied to the CMOS type integrated circuit, inserted into a thermostatic chamber, which is to be tested; failure is detected according to whether the stationary power supply current exceeds a prescribed threshold while the device being tested is in a stable state. In Japanese Patent Laid-open No. 7-5231, a burn-in testing method is described for devices with special structures, such as SOI (Silicon On Insulator) integrated circuits.
In the burn-in testing method described in Japanese Patent Laid-open No. 11-142471, an input test pattern corresponding to the device for testing must be generated, resulting in increased costs. Hence in the case of semiconductor devices for specific applications and semiconductor devices having a variety of functions, the device for testing is inserted into a thermostatic chamber, the power supply voltage alone is applied, and only the change in power supply current is monitored. By applying the power supply voltage in an elevated temperature state, some degree of stress can be applied to the semiconductor device; if the power supply current during accelerated testing remains at a prescribed level the device passes, and if the prescribed level is exceeded the device is judged to be defective owing to the occurrence of some failure. That is, this method cannot reproduce the normal operating state using an input test pattern, and so cannot be described as a complete testing method.
In the case of memory semiconductor devices, writing and reading are repeated while changing the address to perform burn-in testing. In the case of a memory device, data writing and reading operations are verified.
Among semiconductor devices, image sensors having image-capture function, fingerprint sensors and similar must guarantee a prescribed number of operations during use; in the normal state such devices perform no operations, but perform prescribed internal operations in response to an operation command, and thereafter return to the normal state. Hence such semiconductor devices do not have complex logic functions such as those of semiconductor devices for specific applications, nor are writing and reading performed, as in the case of memory devices. For this reason, there have not yet been any proposals of burn-in testing methods appropriate to such semiconductor devices. If a power supply voltage were simply applied to perform accelerated testing, as in the case of the above-described semiconductor devices for special applications, the burn-in tests would be insufficient; and so proposals of appropriate burn-in testing methods have been awaited.
Hence an object of this invention is to provide a method and device to perform burn-in testing appropriate to semiconductor devices such as image sensors and fingerprint sensors.
This invention comprises accelerated testing at normal temperatures as well as at elevated temperatures.